Integrated circuits find application in many of today's consumer electronics, such as cell phones, video cameras, portable music players, printers, computers, calculators, automobiles, etc. Miniaturization of these consumer electronics while providing increased functional integration of memory and logic has long been one of the major drivers within the semiconductor industry. Consequently, manufacturers are turning to three-dimensional (“3D”) packaging to achieve the required high level of functional integration necessary to support these products.
Through silicon vias (TSV's) provide one technique used within the industry for enabling three-dimensional stacking of integrated circuits (ICs), thereby providing the possibility of heterogeneous integration. Additionally, TSV technology offers a reduction in area consumed by the interconnections, while providing shortened electrical pathways with reduced RC delay.
Numerous methods of 3D package fabrication with TSV technology are now known in the art. In one example, a “connecting via” is introduced between the first metal layer of an IC and the TSV contact layer so as to electrically connect the IC devices in the multi-layer, stacked structure. In order to ensure a robust connection, it would be desirable to increase the contact area between the connection via and the TSV. Other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawing figures and the foregoing technical field and background of the invention.